1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a memory cell array chip and an interface chip for changing the memory configuration are stacked.
2. Description of the Related Art
With the miniaturization and increased integration of semiconductor integrated circuits, DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) have achieved memory having greatly increased capacity. However, the miniaturization of semiconductors has limits, and there is consequently a need for the introduction of new techniques for achieving greater increases in capacity.
A three-dimensional semiconductor in which semiconductor chips are stacked has been proposed as one technique for achieving greater capacity. Japanese Patent Laid-Open Publication No. H04-196263 discloses the realization of a large-scale integrated circuit in which semiconductor chips are stacked without changing the chip area. In this circuit, a memory circuit is integrated on a separate chip that is stacked on the main semiconductor integrated circuit. Japanese Patent Laid-Open Publication No. 2002-26283 and Japanese Patent Laid-Open Publication No. 2003-209222 disclose multilayer memory structures in which memory cell arrays are realized with multiple layers to achieve even greater increases in capacity.
In the invention that is described in Japanese Patent Laid-Open Publication No. 2002-026283, memory peripheral circuits are not provided for each memory chip of a multilayered memory chip, but rather, each of the memory chips shares one pair of peripheral circuits to realize a reduction in the area of the peripheral circuits that occupy the chip area.
In the invention that is described in Japanese Patent Laid-Open Publication No. 2003-209222, memory layers can be sorted following fabrication of a multilayered memory device to enable elimination of defective memory layers.
However, although each of the above-described multilayered memory devices enables an increase in memory capacity within a limited chip area, no disclosure is made regarding the number of input/output bits and the number of banks, which are constituent elements of the memory, or regarding the data transfer rate.
On the other hand, the increased performance of the CPU, that accompanies memory, calls for not only greater capacity of the memory device, but also for an increase in the input/output bits, an increase in the number of banks, and a higher memory transfer rate. The diversification of systems has resulted in a wide variety of memory configurations, and as a result, many varieties of memory devices must be developed, and the cost of developing these memory devices grows with each year.